Direct current (DC) to alternating current (AC) power converters are known which use two switching devices connected in series in each leg of a plural leg converter, the junction of each series connected pair of switching devices comprising an output of the converter. Such converters are widely used in adjustable speed AC motor drives where a pulse-width modulated three-phase bridge inverter supplies a voltage of adjustable amplitude and frequency to a motor. When such circuits are operated, care must be taken to assure that only one of the switching devices in each leg of the inverter is conductive at any given time. If both switching devices become simultaneously conductive, a direct short circuit exists across the power lines connected to the switching devices. Many different circuits have been devised for protecting switching devices from destruction by fault current upon such simultaneous conduction. Typically, such protection circuits utilize a choke or inductor serially connected between the inverter and the source of inverter current to limit the rate of rise of fault current. An example of such prior art circuits is shown in W. F. Wirth U.S. Pat. No. 4,331,994 in which an inductor is connected in series with a filter capacitor to limit fault current rise time. In addition, a precharged capacitor, included in a crowbar circuit connected across the DC bus, discharges through the faulted switching devices in a direction opposite to the fault current in order to effect a fast turn-off of the devices.
The amount of current that can be interrupted by power semiconductor switching devices is limited, sometimes by the devices themselves and at other times by auxiliary equipment associated with the devices. In the case of transistors and gate turn-off thyristors, the current limit is set by internal power dissipation. In the case of conventional thyristors, such as silicon controlled rectifiers (SCRs), the limit is set by the size of the auxiliary commutating circuit. Regardless of the type of switching devices used, the available energy which must be discharged through the devices upon a fault condition is generally capable of destroying the devices. This energy discharge mainly arises from DC filter capacitors connected across the power lines to which the switching devices are connected. The DC filter capacitors are provided to limit the DC voltage ripple and at the same time supply the ripple current. If non-electrolytic capacitors are used, the capacitance of the filter capacitors is determined by the allowable voltage excursions. For such conditions, the current rating is more than adequate and the energy stored is minimized so that its discharge during the fault may not present a significant problem. Because the capacitors of a non-electrolytic filter bank are large and expensive, however, electrolytic capacitors are generally used instead if the DC voltage is relatively low, for example, less than 1000 volts. The electrolytic filter capacitor size is determined by the current rating of the component capacitors, which rating is relatively small, and results in much greater capacitance than is needed to limit the voltage ripple. Accordingly, a large amount of energy is stored in a high capacitance and its discharge during faults poses a problem.
An example of one phase of a prior art inverter is shown in FIG. 1. This inverter utilizes a pair of gate turn-off thyristors (GTOs) for switching the direction of current at the output terminal labeled I.sub.out. In order to protect the GTOs from fault currents, a current limiting reactor L.sub.F is inserted into the DC input section of the inverter. Since it is desirable to maintain the reactance or inductance value of the reactor L.sub.F as low as possible, there is also provided a current sensor CT which senses fault currents and applies a signal to a comparator for comparison against a maximum allowable current or trip value. If the fault current exceeds the trip value, a signal from the comparator is applied to a memory circuit which then applies signals to a control circuit to control the gating signals applied by a gate circuit to the controllable switching devices in the inverter. The majority of the fault current is provided by the filter capacitor bank C.sub.F which discharges through the series reactor L.sub.F and the GTOs. A gate driver circuit GD and a snubber circuit SN are also included for controlling operation of the GTOs under normal conditions. The snubber circuit limits the rate of change of voltage during switching of the GTOs.
A disadvantage of the prior art circuit such as that shown in FIG. 1 is that the inductor L.sub.F must be large enough to limit fault current rise time and yet must absorb only a minimum amount of energy during normal operation of the circuit. Ideally, the value of inductor L.sub.F should be small enough that no significant heating effects are observable during normal operation. However, such a design is seldom practical if the value of the reactance of induction L.sub.F is to be sufficiently large to limit fault current through the GTOs.